1. Technical Field
The embodiment described herein relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit which generates a row main signal.
2. Related Art
In general, a row signal path of a dynamic random access memory (DRAM) device receives a row address signal, a word line is selected, and cell data is amplified by a sense amplifier. a row main signal is generated in response to the row address signal and commonly controls row-series circuit units row-series, such as a sub-word line control unit, a sense amplifier control unit, and a bit line equalize control unit.
Since the sub-word line control unit, the sense amplifier control unit, and the bit line equalize control unit commonly receive the row main signal, if the activation timing of the row main signal is changed, the activation timing of the signals associated with these circuit units can also be commonly changed. Accordingly, by appropriately tuning the activation timing of the row main signal, specifications of a RAS to CAS delay time (tRCD) and a precharge to RAS time (tRP), which exist in a corresponding relationship, should meet each other.
However, the tuning of the activation timing of the row main signal is problematic since it requires tuning a delay time for generating a row main signal by opening or closing a switch made of a metal material that connects a plurality of delay elements. For example, when it is necessary to change a metal option so as to meet the specifications of the tRCD and the tRP, mask revisions are required, whereby production time and costs increase.